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74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
September 1991 Revised November 1999
74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ18823 contains eighteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP), Clear (CLR), Clock Enable (EN) and Output Enable (OE) are common to each byte and can be shorted together for full 18-bit operation. The ACTQ18823 utilizes Fairchild's Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector for superior performance.
Features
s Utilizes Fairchild's FACT Quiet Series technology s Broadside pinout allows for easy board layout s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s Extra data width for wider address/data paths or buses carrying parity s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number 74ACTQ18823SSC 74ACTQ18823MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OEn CLRn ENn CPn I0-I17 O0-O17 Description Output Enable Input (Active LOW) Clear (Active LOW) Clock Enable (Active LOW) Clock Pulse Input Inputs Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS010953
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74ACTQ18823
Connection Diagram
Functional Description
The ACTQ18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. The buffered clock (CPn) and buffered Output Enable (OEn) are common to all flip-flops within that byte. The flip-flops will store the state of their individual D inputs that meet set-up and hold time requirements on the LOW-to-HIGH CPn transition. With OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the impedance state. Operation of the OEn input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear (CLRn) and Clock Enable (ENn) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLRn is LOW and OEn is LOW, the outputs are LOW. When CLRn is HIGH, data can be entered into the flip-flops. When ENn is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the ENn is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
Function Table
OE H H H L H L H H L L CLR X X L L H H H H H H
(Note 1) Inputs EN L L X X H H L L L L CP Internal Output On Z Z Z L Z NC Z Z L H Function High Z High Z Clear Clear Hold Hold Load Load Load Load

X X X
In L H X X X X L H L H
Q L H L L NC NC L H L H
H= HIGH Voltage Level L= LOW Voltage Level X= Immaterial Z= High Impedance LOW-to-HIGH Transition NC= No Change

X
=
Note 1: The table represents the logic for one byte. The two bytes are independent of each other and function identically.
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74ACTQ18823
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
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74ACTQ18823
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC +0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current Per Output Pin Junction Temperature PDIP/SOIC Storage Temperature ESD Last Passing Voltage (Min) +140C -65C to +150C 4000V 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA -20 mA +20 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol VIH VIL VOH Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD VOLP VOLV VOHP VOHV VIHD VILD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current Minimum Dynamic Output Current (Note 4) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum Overshoot Minimum VCC Droop Minimum High Voltage Level Maximum Low Dynamic Input Voltage Level 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 5.0 5.0 0.5 -0.5 0.8 -0.8 0.6 8.0 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.5 0.1 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 5.0 1.0 1.5 80.0 75 -75 A A mA A mA mA V V V V V V V Units V V V Conditions VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC -0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 3) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 3) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC -2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min (Note 6)(Note 7) (Note 6)(Note 7) (Note 5)(Note 7) (Note 5)(Note 7) (Note 5)(Note 8) (Note 5)(Note 8)
VOH + 1.0 VOH + 1.5 VOH - 1.0 VOH - 1.8 1.7 1.2 2.0 1.2
Note 3: All outputs loaded; thresholds associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Worst case package. Note 6: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched LOW and one output held LOW. Note 7: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched HIGH and one output held HIGH. Note 8: Maximum number of data inputs (n) switching. (n - 1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
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74ACTQ18823
AC Electrical Characteristics
VCC Symbol fMAX tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ
Note 9: Voltage Range 5.0 is 5.0V 0.5V.
TA = +25C CL = 50 pF Min 100 2.0 2.0 9.0 9.0 9.0 9.0 9.0 7.0 8.0 Typ Max
TA = -40C to +85C CL = 50 pF Min 90 2.0 2.0 2.0 2.0 2.0 1.5 1.5 9.5 9.5 9.5 10.0 10.0 7.5 8.5 Max MHz ns ns ns ns Units
Parameter Maximum Clock Frequency Propagation Delay CPn to On Propagation Delay CLRn to On Output Enable Time Output Disable Time
(V) (Note 9) 5.0 5.0
5.0 5.0 5.0
2.0 2.0 2.0 1.5 1.5
AC Operating Requirements
VCC Symbol tS tH tS tH Parameter Setup Time, HIGH or LOW, Input to Clock Hold Time, HIGH or LOW, Input to Clock Setup Time, HIGH or LOW, Enable to Clock Hold Time, HIGH or LOW, Enable to Clock tW tW tREC CPn Pulse Width, HIGH or LOW CLRn Pulse Width, HIGH or LOW Recovery Time, CLRn to CPn
Note 10: Voltage Range 5.0 is 5.0V 0.5V.
TA = +25C CL = 50 pF Typ
TA = -40C to +85C CL = 50 pF Guaranteed Minimum Units
(V) (Note 10) 5.0 5.0 5.0 5.0
3.0 1.5 3.0 1.5
3.0 1.5 3.0 1.5
ns ns ns ns
5.0
4.0
4.0
ns
5.0 5.0
4.0 6.0
4.0 6.0
ns ns
5
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74ACTQ18823
Extended AC Electrical Characteristics
TA = -40C to +85C VCC = Com Symbol Parameter CL = 50 pF 16 Outputs Switching (Note 12) Min tPLH tPHL tPHL tPZH tPZL tPHZ tPZL tOSHL (Note 11) tOSLH (Note 11) tOSHL (Note 11) tOST (Note 11) Pin to Pin Skew CPn to On Pin to Pin Skew CPn to On Pin to Pin Skew CLRn to Output Pin to Pin Skew CPn to Output Output Disable Time Propagation Delay CPn to On Propagation Delay CLRn to On Output Enable Time 5.2 5.3 4.8 4.2 4.4 3.5 4.6 Typ 6.5 6.5 5.3 4.8 5.3 4.2 5.2 Max 7.6 7.8 6.2 6.5 6.0 4.8 6.0 1.0 1.0 1.0 1.5 Min 7.0 6.8 5.2 (Note 14) (Note 15) TA = -40C to +85C VCC = Com CL = 250 pF (Note 13) Max 9.8 10.0 7.5 ns ns ns ns ns ns ns ns Units
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (il.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 14: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 15: The Output Disable Time is dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol CIN CPD Parameter Input Pin Capacitance Power Dissipation Capacitance Typ 4.5 95 Units pF pF VCC = 5.0V VCC = 5.0V Conditions
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74ACTQ18823
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and affect the results of the measurement. VOLP/VOLV and VOHP/VOHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. * Next decrease the input HIGH voltage level, VIH, until the output begins to oscillator steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD.
VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
* Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ18823
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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